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Infineon

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Design Methodology & Flow Timing Expert @ Infineon

1. Working with the team of SOC design methodology, flow and implementation engineers. 2. Work on Synthesis, STA, DFT, Spyglass and timing constraints development for complex designs. 3. Develop fullchip/interfaces timing constraints with several IPs for functional and test modes interacting with RTL designers and understanding design specification. 4. Responsible for full chip timing closure for all modes and timing characterization of IO interfaces. 5. Work closely with Timing methodology/signoff team and design teams to improve the flow which helps faster timing closure. 6. Responsible for debugging current tool and flow issues working closely with EDA vendors and drive them for new features. 7. Adapting Infineon flow and tools for faster and reliable tape out of complex designs. Work as integral part of the team in Global environment. 8. Help, assist, resolve technical issues for flow/designs across all sites. 9. Work with Design and flow teams to understand the drawbacks with the current flow/methodology. Propose new methodologies to reduce the design cycle time. Desired Profile Please refer to the Job description above Experience 8 - 13 Years Industry Type Semiconductors / Electronics Role Technical Architect

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IFINRecruitment@infineon.com

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