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Cadence Design Systems Inc.

To keep pace with market demand for more performance and functionality in today’s mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip’s transistors and other physical features can be smaller than the wavelength of light used to print them.Designing and manufacturing semiconductor devices with su... Read More

Address      Bagshot Road Bracknell Berkshire, RG12 OPH United Kingdom
Website      www.cadence.com/
Holding      No Holding Details

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Product Engineer

As a Verification Engineer in Cadence’s Design IP Division, candidate will contribute building Advanced Verification Methodologies with focus on SystemVerilog and SystemC based implementations. Duties will include functional verification environment architecture and setup, development of UVM based Verification environments as well as setup EDA tools (HAL, NCSIM, Simvision, RTL Compiler, Conformal etc) environment as part of developing design IP process.

Position Requirements

7+ years as a Verification Engineer
Extensive experience in creating Coverage Driven Verification environments utilizing e, SystemVerilog or SystemC/C++ is required
Track record of successfully verifying complex ASICs is also required
Languages: SystemC, C++, SystemVerilog, Specman
Methodologies: Preferable experience in ERM, OVM or VMM
Experience with Memory subsystem verification environments (DDR)
Experience in process automation with PERL or Tcl scripting is required
Education: BSEE. MSc preferred

Other Job Information

Vacancy type:

Full Time

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