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Ansys Apache India Private Limited

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Website      www.apache-da.com/
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Sr. R&D Engineer ( Physical Layout Modeling )

Position Summary: The ANSYS Apache, Bangalore R&D team is looking for a middle level independent developer cum lead to help design and architect core in-memory C++ software. As a member of the team, you will be involved in mentoring an agile, fast paced team that produces physical layout modeling, design exploration and generates software that supports ANSYS Apache flagship products. Essential Job Functions/Accountabilities: The focus would be to develop, own and lead a fast, robust and high quality C++ based tool with performance and capacity optimization with applying efficient and high capacity data structures. Salary: Comparable to best in the Industry Industry: IT-Software / Software Services Functional Area: IT Software - Embedded, EDA, VLSI, ASIC, Chip Design Role Category: Programming & Design Role: Software Developer Education: (UG - B.Tech/B.E. - Computers, Electrical, Electronics/Telecommunication) OR (PG - M.Tech - Computers, Electrical, Electronics/Telecommunication) OR ( Doctorate - Doctorate Not Required) Minimum Requirements/Qualifications: A BE/BTech/MTech in CSE/EE Having Excellent academic background from premium institutes Min 2 to 3 years of software development experience in EDA Good understanding of digital design / EDA flow Other Job Requirements: Proven proficiency in C++ programming language and data structures into EDA development environment Sound understanding of algorithm, DS and implementation of large data handling and processing Independent developer to own modules and can deliver code independently Ability to mentor junior R&D Engineers Non-Negotiable Hiring Criteria: ANSYS INSPIRE Values: Innovation Strive for Excellence Passion & Intensity Integrity Respect & Trust

Other Job Information

Vacancy type:

Full Time

Contact Mode:

Plot No. 31/1, Rajiv Gandhi Infotech Park, M.I.D.C


not provided

Contact Name:

Payal Tyagi

Job Duration:

not provided


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